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The current mainstream 4G RF front-end architecture mostly adopts TRX (receive path + transmit path) + DRX (diversity reception) to achieve 1T2R mode, and both TRX and DRX paths are implemented by integrated modules. Simply put, each frequency band is integrated into 6~8 modules according to the frequency, namely GSM/LB/MB/HB
PAMID modules and GSM/LB/MB/HB Diversity FEM modules. And 5G needs to increase the radio frequency front-end device to match it, at least need to add channels corresponding to the two frequency bands n78/n79, which is 1T4R under the NSA standard and 2T4R under the SA standard.

5G introduces functions such as 4*4
MIMO , SRS and EN-DC , which requires the receiving end of the RF front-end to have the ability to receive four channels in a single frequency band . Compared with the two-channel receiving solution used in 4G, the price has increased by 229%.

Taking domestic 5G mobile phones as an example, high-end models generally use the 221 solution, that is, 2-way N41, 2-way N78 and 1-way N79 main set chip, and the receiving end needs additional 2-way N41, 2-way N78 and 3-way N79 diversity chips accordingly. ; The 211 scheme is generally used at the transmitter end of low-end models, that is, 2-way N41, 1-way N78 and 1-way N79 main set chip, then the receiving end needs an additional 2-way N41, 3-way N78 and 3-way N79 diversity chip. Most of the main chips use the PAMid solution, and the suppliers are Qualcomm, Qorvo, and Sky from abroad; the diversity chips are the biggest opportunity for domestic manufacturers, and domestic Zhuoshengwei, Weijie, and Onray are expected to enter the domestic Tier1
OEM supplier list . The hardware architecture of the baseband chip adopts the form of MCU+DSP+ASIC . The hardware is the body of the baseband chip and determines the lower limit of the baseband performance.        

The MCU is mainly used to run the code of the baseband protocol stack. At present, the mainstream baseband MCUs mostly use the ARM core, mainly the Cortex A series and the Cortex R series. In addition, in order to reduce the power consumption of the baseband chip, an additional Cortex
M will be used as the MCU of the baseband chip in low-power scenarios such as flight mode and standby;
        

DSP is the core hardware of the baseband chip, which is used to implement the core algorithm of the wireless communication physical layer (L1). The main functions are codec, FFT/iFFT, CRC check, etc. DSP determines the data throughput capacity of the baseband chip. DSP has two types: self-developed and IP licensing. Qualcomm, MTK, and HiSilicon use self-developed solutions, and other manufacturers use Ceva's IP licensing;

ASIC includes the realization of auxiliary functions such as the internal debugging interface of the baseband chip and the peripheral interface. This type of chip has low complexity and generally adopts the method of IP authorization.

Baseband chip software mainly includes real-time operating system (RTOS), drivers (Drivers) and protocol stack (Protocol
Stack). The protocol stack is the core of the baseband software. Software is the soul of the baseband chip and determines the upper limit of the chip's performance.